Metal-Oxide-Semiconductor (MOS) transistors have become the most important and essential electronic units in the field of current VLSI technologies. With the more and more complicated circuitry, the included MOS transistors are significantly increased so that to develop a technology that allows more electronic devices to be installed on a chip having a confined area to comply with the high density requirement is an urgent issue for semiconductor manufacturing, from which a few problems are derived.
For the fabrication of a chip having a high device density thereon, it is essential to reduce the size of the devices to be arranged on the chip. For a MOS transistor, when its size is reduced, the channel length thereof is also shortened and meanwhile the operation speed thereof is increased. The channel length, however, cannot be shortened infinitely because the so-called "short channel effects" will occur when the channel length is shortened to a certain extent. The short channel effects include the drop of the threshold voltage (Vt) and the carrier multiplication due to hot electron effects, finally resulting in the electrical breakdown phenomenon.
In the prior art, an implantation step for threshold voltage adjustment is performed prior to the formation of the gate structure to avoid the drop of the threshold voltage mentioned above. Please refer to FIGS. 1(a).about.1(e) which are schematic diagrams showing, the respective steps of a conventional process for fabricating an N-channel MOS transistor. The chip shown in FIG. 1(a) is a p-type silicon chip which has been treated with procedures of washing, thermal oxidization and micro-lithography. The resulting chip is implanted with boron atoms as an implant source at an active area 111 thereof for threshold voltage adjustment, and then field oxide layers 112 and 113 are grown on the chip by wet oxidation. Afterwards, the silicon atoms distributed on the top face of the washed active area 111 are formed as a gate oxide layer 114 by dry oxidation, and a gate structure 115 is further formed above the gate oxide layer 114, as shown in FIG. 1(b). The gate structure 115 is formed by depositing a layer of polysilicon on the whole surface of the chip by a low-pressure chemical vapor deposition (LPCVD) process, doping VA group impurities in the is periodic table such as P or As into the polysilicon layer in a high concentration by a thermal diffusion or an ion implantation process to reduce the resistivity, washing the resulting chip with a solution containing hydrogen fluoride, depositing a silicide layer (preferably a tungsten silicide layer) on the washed chip, defining the gate structure 115 by a micro-lithographic process, and then performing an annealing process to obtain the construction as shown in FIG. 1(b).
Afterwards, VA group impurities in the periodic table such as phosphorous atoms are implanted with the resulting grate serving as a mask, The concentration of the impurities implanted in this step is relatively low, and it is controlled at an amount of about 10.sup.13 per cubic centimeter. Accordingly, lightly doped drain (LDD) regions 116 as shown in FIG. 1(c) is formed to prevent the short channel effects in the prior art. Further, a silicon oxide layer is deposited by a CVD process, then the resulting chip is transferred to a thermal diffusion oven for the diffusion of the phosphorous atoms, and a part of the silicon atom structure on the surface of the chip, which is damaged in the impurity implantation process, is annealed at the same time. Now referring to FIG. 1(d), gate side walls 117 are obtained by an anisotropic etching process. Subsequently, VA group impurities in the periodic table such as arsenic atoms are heavily doped with the gate side walls and the gate electrode serving as a mask to form the main portions of a source and a drain electrodes, as shown in FIG. 1(e). The impurity concentration implanted in this step is controlled at an amount of about 10.sup.15 per cubic centimeter. As known to those skilled in the art, in the manufacturing process for a semiconductor device, the more the steps required in the process, the more the variables and the lower the yield. In addition, the production efficiency will be adversely effected and the manufacturing cost will be improperly increased if too many steps have to be performed in the manufacturing process. Therefore, the reduction of the number of steps required in a manufacturing process for a semiconductor device without deteriorating the semiconductor device is the goal of the present research and development.